To satisfy the demand for large scale digital integrated circuits, the semiconductor industry has developed three basic approaches. These include standard, off the shelf circuits; custom circuits; and semicustom arrays. The standard, off the shelf circuit provides the lowest cost option due to the quantities manufactured, but are limited in providing the flexibility for the circuit desired. The custom circuit is cost limiting unless the number of circuits desired is large. The semicustom array involves a standard array of a large number of gate circuits diffused into a chip. The metallization pattern converting these gate circuits into functional custom circuits is processed according to the customer's requirement.
Semicustom design of arrays provides the advantages as follows: the choice of specific combinations of functions on a chip; reduced lead time in requesting the finished product; cost reduction by reducing component count, power and board size; and enhancing system functions and reliability.
Semicustom arrays include both gate arrays and standard cell arrays. Gate arrays begin as a collection of unconnected transistors and resistors. Designers specify how the transistors and resistors will be interconnected according to the logic needs of a particular project.
A standard cell is a predesigned functional block that performs a specific logic function. A standard cell array comprises many of these functional blocks. A number of standard cells performing different functions are typically stored in a library. Design engineers select the combination of cells they need for an integrated circuit. The density of functions for the standard cell array is higher on the component than the gate array, and there are fewer unused transistors and interconnect areas. Standard cells also allow the designer to integrate analog and digital functions on a single chip. A standard cell library typically comprises gates (i.e., AND, OR), flip-flops (i.e., latches), special functions (i.e., voltage references, shift registers), input/output cells (i.e., three state), analog cells (i.e., oscillators, operational amplifiers), memory cells (i.e., RAM) and microcomputers.
A gate array core cell comprises a specific number of MOSFET transistors, typically eight, that are interconnected by a first of two or three layers of metal to form a specific function know as a macro cell. The second and third layer of metal are used to connect the plurality of macro cells to form a specific logic system. Each signal from transistor to transistor or from cell to cell is transferred by a metal strip within one of the metal layers. Each metal strip in a gate array is located in a routing channel. A routing channel is a dedicated area on the chip.
Conventionally, routing channels are predefined for consideration by the circuit designer. A more efficient gate array conventionally use two designs, sea-of-gates and channelless. The sea-of-gates design includes no routing channels and has metal routed over unused cells, as well as through used cells. About sixty percent of the cells are typically unusable for the sea-of-gates design. The channelless design includes no routing channels wherein metal is routed through unused cells. About forty percent of the cells are typically unusable for the channelless design.
Thus, what is needed is a core cell having improved device isolation, internal routing channels, shared power busses, and customized metal routing under power busses that provides for more efficient use of available cells.